1. Technical Field
Embodiments of the inventive concept relate to a semiconductor device, and more particularly, to a circuit for controlling an on-die termination latency clock of a semiconductor memory device.
2. Discussion of Related Art
When semiconductor devices operate at high speeds, a swing width of interfaced signals communicated between the devices may be reduced to lessen a delay experienced in the communication. However, reducing the swing width may cause the signals to be more greatly affected by fluctuations in external noise, which may result in mismatching of impedances. The mismatching of impedances may also be caused by a fluctuation in a power voltage, a change in an operation temperature, the manufacturing process, etc.
The mismatching of impedances may adversely affect transmission of data at high speeds or data distortion when data is output from semiconductor devices.
Semiconductor devices that operate at high speeds may include an impedance matching circuit including an on-die termination (ODT). The ODT may receive an ODT signal to trigger an ODT operation therein.
A Dynamic random access memory (DRAM) may include an ODT latency circuit and an ODT latency clock generation circuit to delay the ODT signal. The ODT latency circuit is controlled by ODT latency clocks generated by the ODT latency clock generation circuit.
However, even when an operation of the ODT latency clock generation circuit is unnecessary, the ODT latency clock generation circuit operates, which may increase the amount of power used by the ODT latency circuit and the ODT latency clock generation circuit.